| Designer | Intel |
|---|---|
| Design | manycore extended x86/x64 design |
| Registers | |
| General purpose | Intel Architecture registers |
| Floating point | 512-bit SIMD vector registers |
Intel Many Integrated Core Architecture or Intel MIC (pronouced Mike) is a multiprocessor computer architecture developed by Intel incorporating earlier work on the Larrabee multicore architecture, the Teraflops Research Chip multicore chip research project and the Intel Single-chip Cloud Computer multicore microprocessor.
Prototype products, codenamed Knights Ferry were announced and released in 2010 to developers including CERN, Korea Institute of Science and Technology Information (KISTI) and Leibniz Supercomputing Centre. Hardware vendors for prototype boards included IBM, SGI, HP, Dell and others.[1]
A commercial release, codenamed Knights Corner to be built on a 22nm process is proposed for release late 2012 to 2013. In September 2011 it was announced that the Texas Advanced Computing Center (TACC) will use Knights Corner cards in their 10 PetaFLOPS "Stampede" supercomputer, providing 8 PetaFLOPS of the compute power.[2]
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The Larrabee microarchitecture (in development since 2006[3]) introduced very wide (512-bit) SIMD units to a x86 architecture based processor design, extended to a cache coherent multiprocessor system connected via a ring bus to memory; each core was capable of 4-way multi-threading. Due to the design being intended for GPU as well as general purpose computing the Larrabee chips also included specialised hardware for texture sampling.[4] The project to produce a GPU retail product directly from the Larrabee research project was terminated in May 2010.[5]
Another contemporary Intel research project implementing x86 architecture on a many-multicore processor was the 'Single Chip Cloud Computer', (prototype introduced 2009.[6]), a design mimicking a cloud computing computer datacentre on a single chip with multiple independent cores - the prototype design included 48 cores per chip with hardware support for selective frequency and voltage control of cores to maximise energy efficiency, and incorporated a mesh network for interchip messaging. The design lacked cache coherent cores and focussed on principles that would allow the design to scale to many more cores.[7]
The Teraflops Research Chip (prototype unveiled 2007.[8]) was an experimental 80 core chip with two floating point units per core implementing a 96-bit VLIW architecture. The project investigated intercore communication methods, per-chip power management, and achieved 1.01 TFLOPS at 3.16 GHz consuming 62 W of power.[9][10]
Intel's MIC prototype board, named Knights Ferry, incorporating a processor codenamed Aubrey Isle was announced 31 May 2010. The product was stated to be a derivative of the Larrabee project and other Intel research including the Single-chip Cloud Computer.[11]
The development product was offered as a PCIe card with 32 in-order cores at up to 1.2 GHz with 4 threads per core, 2 GB GDDR5 memory,[12] and 8 MB coherent L2 cache (256 kB per core with 32 kB L1 cache),[13] and a power requirement of ~300 W,[12] built at a 45 nm process.[14] In the Aubrey Isle core a 1,024-bit ring bus (512-bit bi-directional) connects processors to main memory.[15] Single board performance has exceeded 750 GFLOPS.[14] The prototype boards only support single precision floating point instructions.[16]
The Knights Corner product is expected to be made at a 22 nm process size, using Intel's Tri-gate technology with more than 50 cores per chip, and is expected to lead to commercial products.[11][14]
In June 2011, SGI announced a partnership with Intel to utilize the MIC architecture in its high performance computing products.[17] In September 2011, it was announced that the Texas Advanced Computing Center (TACC) will use Knights Corner cards in their 10 PetaFLOPS "Stampede" supercomputer, providing 8 PetaFLOPS of the compute power.[2] According to "Stampede: A Comprehensive Petascale Computing Environment" the "second generation Intel (Knights Landing) MICs will be added when they become available, increasing Stampede's aggregate peak performance to at least 15 PetaFLOPS."[18]
On November 15, 2011, Intel showed a Knights Corner processor publicly for the first time. It was an early silicon sample. Intel also demonstrated that it was very functional by setting a world record 1 TeraFLOPS of performance for a general purpose processor. The Knights Corner demo showed sustained performance of more than a TeraFLOPS on a wide range of DGEMM operations. Intel emphasized during the demonstration this represented sustained TeraFLOPS (not "raw TeraFLOPS" used by others to get higher but less meaningful numbers), and that it was the first general purpose co-processor to ever achieve TeraFLOPS performance.[19][20]
Code name for the second MIC architecture processors from Intel.[21][22]
Intel MIC is designed to compete directly with Nvidia Tesla product line in the HPC market.[23] Within four years since launch, Tesla co-processors have experienced growing adoption in the HPC community, demonstrated in the November 2011 Top500 list where number of Tesla GPU powered systems grew to 35, more than 2x increase in six months.[24] And for two years running, Tesla GPUs are powering the "greenest" petaflop system in the Green500 list.[25] Recently, Chinese researchers have reported using Tesla GPUs to simulate the world's largest molecular dynamics simulation of 110 billion atoms at 1.87 petaflops and to simulate world's first complete H1N1 virus model.[26][27]
The basis of the Intel MIC design is to leverage x86 legacy by creating a x86 compatible multiprocessor architecture that can utilise existing paralellisation software tools.[14] Programming tools include OpenMP, OpenCL,[28] Intel Cilk Plus and specialised versions of Intel's Fortran, C++ and math libraries.[29]
Design elements inherited from the Larrabee project include x86 ISA, 512-bit SIMD units, coherent L2 cache, and ultra-wide ring bus connecting processors and memory.